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TK75001
PWM CONTROLLER FEATURES
s s s s s s s s Optimized for Off-Line Operation Maximum Duty Ratio 44% (typ.) Maximum Clock Frequency Above 1 MHz Frequency Reduction for Improved Overcurrent Protection Low Standby Current for Current-Fed Start-Up Current-Mode or Voltage-Mode Control Internal User-Adjustable Slope Compensation Functionally Integrated & Simplified 5-pin Design
APPLICATIONS
s s s s Off-Line Power Supplies Industrial Power Supplies Telecom Power Supplies Off-Line Battery Chargers
DESCRIPTION
The TK75001 is a simplified primary side controller optimized for off-line switching power supplies. It is suitable for both voltage-mode and current-mode control and has advanced features not available in controllers with a higher pin count. The key to full functionality in a 5-pin design is that the current signal and the error signal are added together and fed into the feedback pin. A sawtooth current flowing out of the feedback pin provides a slope compensation ramp (in current-mode applications) or a PWM ramp (in voltage-mode applications), in proportion to the resistance terminating that pin. If the sum of the current sense signal, error signal and ramp signal exceeds the Overcurrent Detector threshold indicating that the Current Control Detector has lost control of the switch current, the charging current of the timing capacitor will be reduced to about 25% for the remainder of the clock period. The reduced charging current causes no more than a one-third reduction in switching frequency, effectively preventing short-circuit current runaway.
CT
TK75001
DRV
VCC NC NC
GND
7500 1
GND CT
FB
Note: Pins 2 and 3 must be externally connected for proper operation.
BLOCK DIAGRAM
VCC ICT BANDGAP REFERENCE 14.5 V 10.5 V OSCILLATOR IFR 146 A IDS 2 mA fCLK 17.5 V UVLO ICHG 205 A
The TK75001 is available in an 8-pin DIP package.
ORDERING INFORMATION
Q
R FREQUENCY REDUCTION LATCH S
TOGGLE FF T Q
TK75001D
Tape/Reel Code Temperature Code
SLOPE COMPENSATION
PWM LATCH S Q R DRV
OVERCURRENT DETECTOR 1.35 V
TEMP. CODE (OPTIONAL)
I: -40 to +85 C
TAPE/REEL CODE
MG: Magazine
FB 0.98 V
CURRENT CONTROL DETECTOR
GND
January 1999 TOKO, Inc.
Page 1
TK75001
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low Impedance Source) ................ 16 V Supply Voltage (ICC < 30 mA) ...................... Self Limiting Power Dissipation (Note 1) ................................ 825 mW Output Energy (Capacitive Load) .............................. 5 J CT and FB Pins ........................................................ 16 V Junction Temperature ........................................... 150 C Storage Temperature Range ................... -55 to +150 C Operating Temperature Range ...................-20 to +80 C Extended Temperature Range ................... -40 to +85 C Lead Soldering Temperature (10 s) ...................... 235 C
TK75001 ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 13 V, CCC = 4.7 F, CT = 800 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range. Typical numbers apply at TA = 25 C, unless otherwise specified.
SYMBOL ICC(START) ICC(ON) VCC(ON) VCC(OFF) VHYST VCC(CLAMP)
PARAMETER Start-up Supply Current Operating Supply Current UVLO Voltage ON UVLO Voltage OFF UVLO Hysteresis Internal Clamp Voltage
TEST CONDITIONS Current Source to VCC Pin
MIN
TYP 0.5 14.5
MAX 1.0 19.0 16.0 12.0
UNITS mA mA V V V
VCC Sweeps Upward, (Note 3) VCC Sweeps Downward
12.5 9.0 2.8
14.5 10.5 4.0 17.5
ICC = 25 mA, (Note 3)
16.0
19.0
V
OSCILLATOR SECTION (CT PIN) fDRV VCT(PK) VCT(VL) ICT(DIS) CT(MAX) Frequency at DRV Pin Peak Voltage Valley Voltage Discharge Current Maximum Timing Capacitance 1.0 4.7 TA = Tj = 25 C TA = Tj = Full Range (-20 to 80 C) 44 37 2.5 3.2 1.1 1. 8 3.0 50 56 63 3.9 kHz kHz V V mA nF
CURRENT DETECTOR, FEEDBACK AND FREQUENCY REDUCTION SECTIONS (FB PIN) VCCD Current Control Detector Reference Voltage Overcurrent Detector Reference Voltage Propogation Delay to DRV Pin Propogation Delay to DRV Pin Slope Compensation Peak Current Slope Compensation Valley Current Slope Compensation Peak to Valley TA = Tj = 25 C TA = Tj = Full Range (-20 to 80 C) TA = Tj = 25 C TA = Tj = Full Range (-20 to 80 C) VFB Steps from 0 to 2 V VFB Steps from 0 to 1.20 V, (Note 4) VCT = VCT(PK), TA = Tj = 25 C, (Note 2) VCT = VCT(VL), TA = Tj = 25 C, (Note 2) VCT = VCT(VL), TA = Tj = 25 C, (Note 2) -245 -65 -200 0.950 0.925 1.320 1.305 60 80 -200 -40 -160 1.350 0.980 1.010 1.035 1.380 1.395 130 180 -155 -15 -120 V V V V ns ns A A A
VOCD tFB,OC,PD tFB,CC,PD iSC(PK) iSC(VL) iSC(PK-VL)
Page 2
January 1999 TOKO, Inc.
TK75001
TK75001 ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: VCC = 13 V, CCC = 4.7 F, CT = 800 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range. Typical numbers apply at TA = 25 C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FREQUENCY REDUCER (OVERCURRENT PROTECTION TIMING) fDRV(FR) / fDRV Frequency Reduction Ratio VFB = 1.2 V, 1.6 V 35 46 55 %
OUTPUT SECTION (DRV PIN) DDRV(MAX) tDRV(RISE) tDRV(FALL) VDRV(HIGH) Maximim Duty Ratio Rise Time Fall Time Output Voltage HIGH 1000 pF load, VCC = 15 V 1000 pF load, VCC = 15 V IDRV = -40 mA IDRV = -100 mA IDRV = 40 mA VDRV(LOW) Output Voltage LOW IDRV = 100 mA IDRV = 5 mA, VCC = 9 V
Note 1: Note 2: Note 3: Note 4: Power dissipation is 825 mW when mounted. Derate at 6.6 mW/C for operation above 25 C. For temperature dependence refer to "Slope Compensation Peak Current vs. Temperature" graph. The UVLO "on" voltage is guaranteed to be below the internal clamp voltage. Guaranteed by design; not 100% tested.
40
44 25 25
48 75 75
% ns ns V V
10.1 10.0
11.0 10.8 0.1 0.2 1.0 0.25 0.50 1.50
V V V
January 1999 TOKO, Inc.
Page 3
TK75001
TEST CIRCUIT
DRV
VCC
GND OSCILLOSCOPE GND
NC 1 F NC
CCC 4.7 F
1000 pF
CT
FB
OSCILLOSCOPE CT 800 pF
20 k
TYPICAL PERFORMANCE CHARACTERISTICS
VS.
SUPPLY CURRENT SUPPLY VOLTAGE 106
FREQUENCY AT DRV PIN VS. TIMING CAPACITANCE TA = -40 C
1.00 0.98
CURRENT CONTROL REFERENCE VS. TEMPERATURE
20 16
ICC (mA)
DEVICE ON
FREQUENCY (Hz)
12 0.6 STANDBY 0.4 0.0
TA = 85 C 104
VCCD (V)
105
0.96 0.94 0.92
0
4
8
12
16
18
103 10
100
1000 CT (pF)
10000
0.90
-40
0
40
80
120
VCC (V)
SLOPE COMPENSATION PEAK CURRENT VS. TEMPERATURE -100 30
TEMPERATURE (C)
INPUT CURRENT VS. FREQUENCY AT DRV 54
FREQUENCY REDUCTION RATIO VS. TEMPERATURE
FREQ. REDUCTION RATIO (%)
50 48 44 40 36
iSC(PK) (A)
-180
ICC (mA)
-140
26
CDRV = 1 nF
22
CDRV = 500 pF
-220
18 CDRV = 0 nF
-260
-40
0
40
80
120
14
0
200
400
600
800
-40
0
40
80
120
TEMPERATURE (C)
FREQUENCY (kHz)
TEMPERATURE (C)
Page 4
January 1999 TOKO, Inc.
TK75001
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
SLOPE COMPENSATION RAMP RFB = 3 k to GND CT = 800 pF
600 450
VFB (mV)
300 150 0 0 10 20 30 TIME (s) 40 50 60
January 1999 TOKO, Inc.
Page 5
TK75001
THEORY OF OPERATION
The TK75001 is intended for use as a primary-side Pulse Width Modulator (PWM) controller. The many features integrated into a simple 5-pin design allow it to be easily configured for voltage-mode or current-mode control, fixedfrequency or fixed-off-time operation, off-line bootstrapping, and direct drive of a power MOSFET. The polarity of the feedback signal allows for simpler interface with a TL431-derived error signal (see "Applications Information" section). The most noteworthy integrated feature in the TK75001 is the way in which the feedback control pin is configured to receive the error signal and the current signal for currentmode control. Rather than receiving both inputs into a comparator, a single input receives both signals summed together and compares them against a fixed internal reference. This yields two desirable effects: 1) a currentlimit threshold is automatically established, and 2) the required error-signal polarity is the inverse of that of a standard two-input current-mode control system. Generally, the signal summation requires no additional external components and the required error-signal polarity is simpler to achieve. Two other functions are integrated into the feedback pin. A current ramp, which can be used to establish either the slope-compensation ramp for a current-mode control design or the voltage-comparison ramp for a voltage-mode control design, flows out of the feedback pin. By adjusting the terminating resistance at the feedback pin, the desired ramp magnitude is established. For overcurrent protection, a second fixed-reference comparator monitors the feedback pin. If the feedback pin voltage should reach the second threshold, this indicates that cycle-by-cycle PWM control is not sufficient for maintaining control of the current (i.e., the minimum duty-ratio is too large to achieve volt-second balance in the magnetics). The overcurrent detection comparator latches (for one cycle) a reduction in the source current which feeds the timing capacitor. This has the effect of reducing the switching frequency and thus, effectively, the minimum duty ratio, which is just what is needed to maintain control of the current. The switching frequency is determined by an internal current source charging an external timing capacitor. The timing capacitor is ramped between internally-fixed thresholds, valley to peak, and then quickly discharged. A fixed off-time control technique can be readily implemented by using a small transistor to keep the timing capacitor discharged during the on-time. When the on-pulse is Page 6 January 1999 TOKO, Inc. terminated, the timing capacitor ramps up to a fixed threshold at a fixed rate to fix the off-time. The Undervoltage Lockout (UVLO) feature with hysteresis minimizes the start-up current which allows a low-power bootstrap technique to be used for the housekeeping power. The duty ratio of the TK75001 is limited to less than fifty percent by a toggle flip-flop, plus time required to discharge the timing ramp.
TK75001
PIN DESCRIPTIONS
SUPPLY VOLTAGE PIN (VCC) This pin is connected to the supply voltage. The IC is in a low current (500 A typ.) standby mode before the supply voltage exceeds 14.5 V (typ.), which is the upper threshold of the UVLO circuit. The IC switches back to standby mode when the supply voltage drops below 10.5 V (typ.). An internal clamp limits the peak supply voltage to about 17.5 V (typ.). The absolute maximum supply voltage from a low impedance source is 16 V. The device is always guaranteed to turn on before the internal clamp turns on. GROUND PIN (GND) This pin provides ground return for the IC. DRIVE PIN (DRV) This pin drives the external MOSFET with a totem pole output stage capable of sinking or sourcing a peak current of about 1 A. In standby mode, the drive pin can sink about 5 mA while keeping the drive pin pulled down to about 1 V. The maximum duty cycle of the output signal is typically 44%. TIMING CAPACITOR PIN (CT) The external timing capacitor is connected to the CT pin. That capacitor is the only component needed for setting the clock frequency. The frequency measured at the CT pin is twice the frequency measured at the DRV Pin. The maximum recommended clock frequency of the device is 1.6 MHz. At normal operation, during the rising section of the timing-capacitor voltage, a trimmed internal current of 205 A flows out from the CT pin and charges the capacitor. During the falling section of the timing-capacitor voltage an internal current of about 1.8 mA discharges the capacitor. If the voltage at the feedback(FB) pin exceeds 1.35 V (e.g., due to the turnoff delay during a short-circuit at the output of a converter using the IC), the charging current is reduced to about 59 A, leading to a 2.17-fold reduction in switching frequency. The frequency reduction is useful for preventing short-circuit current runaway. FEEDBACK PIN (FB) The feedback pin receives the sum of three signals: the error signal (from the external error amplifier), the switch current signal and a voltage ramp generated across the terminating resistance by an internal sawtooth-shaped January 1999 TOKO, Inc. Page 7 current with a peak value of about 200 A. The error signal is needed for stabilizing the output voltage or current. The switch current signal is needed in current-mode controlled converters and in converters with cycle-by-cycle overload protection. Also, the switch current signal is required for detecting impending short-circuit current runaway, and for initiating a frequency reduction for preventing the runaway. The voltage ramp is needed for slope compensation in current-mode controlled converters, or for pulse-width modulation in voltage-mode controlled converters. At higher clock frequencies, the bandwidth limitation of the internally-generated sawtooth-shaped current source becomes more apparent. The degree to which ramp bandwidth is tolerable depends on performance requirements at narrow pulse widths. A low impedance at the feedback pin can effectively eliminate the internallygenerated ramp effects, and an external ramp can be readily created to attain higher performance at high frequencies, if desired.
TK75001
DESIGN CONSIDERATIONS
SELECTING A START-UP RESISTOR Figure 1 shows the typical application of the TK75001 in an off-line flyback power supply (input full-wave bridge and capacitor not shown). The IC starts when the voltage across the capacitor CAUX reaches the UVLO on Voltage VIN(ON) of the IC. The starting resistor RST can be designed as follows: considering the component tolerances, ripple, and other second-order effects. The upper limit for VAUX is the minimum voltage of the built-in clamp (16 V). The lower limit for VAUX is the maximum UVLO off voltage (12.0 V). It is prudent to choose the mean value of those two voltages (i.e., 14.0 V), as VAUX. COMPENSATING FOR LEAKAGE INDUCTANCE The leakage inductance of the flyback transformer causes a voltage overshoot at turn-off of the MOSFET. The magnitude and duration of the overshoot depends on the leakage inductance, the peak current at turn-offs, and the voltage-clamping circuit employed to limit the overshoot. The overshoot tends to increase the auxiliary voltage. The simplest solution to reduce that increase is to add a resistor RAUX in series with the rectifier diode D3. The optimal value of the resistor can be calculated from the subcircuit shown in Figure 2. The average current flowing in RAUX is equal to the current IAUX drawn by the IC. The following equation can be written from the equality:
RST(MAX) = (VIN(MIN) - VCC(ON,MAX) - 2 V) / ICC(START, MAX) (1) At 85 Vrms line voltage, and taking into account the specified maximum values of the UVLO on voltage and the start-up supply current ICC(START), the maximum allowed value of the starting resistor is:
RST(MAX) = (85 (2)
2 - 16 - 2 ) / 1.0 mA = 102.2 k
A practical choice for the starting resistor is R ST = 100 k. The worst-case dissipation of the resistor appears at high line and at the minimum VCC voltage. At 265 Vrms line voltage and 9 V VCC, the dissipation is 2.2 W, so a 3 W resistor should be used. Note that 1.0 mA reflects the worst case ICC(START) at the edge of UVLO release. SELECTING THE TRANSFORMER TURNS RATIO During steady-state operations, the auxiliary supply voltage is generated by the auxiliary winding n3 and the rectifier diode D3. In the flyback power supply, neglecting the effect of the leakage inductance of the transformer, the number of turns of the auxiliary winding can be calculated from the following equation:
IAUX = (1 / RAUX) x ([(V1 - VD3 - VAUX) x (T1 / T)] + [(V2 - VD3 - VAUX) x (T2 / T)])
(4) The voltage V1 can be calculated as follows: V1 = (VOUT + VD2) x (n1 / n2) + [VOVERSHOOT x ( n3 / n2)] (5) where VOVERSHOOT is the additional voltage appearing across the MOSFET due to the leakage inductance. The voltage V2 can be calculated as follows:
n3 = n2 [(VAUX + VD3) / (VOUT + VD2)] (3) where VD2 and VD3 are the forward voltage drops of the output rectifier diode and the auxiliary rectifier diode. The voltage VAUX should be selected such that it stays between the specified worst-case upper and lower limits of the IC, Page 8 (6) V2 = (VOUT + VD2) x ( n3 / n2)
January 1999 TOKO, Inc.
TK75001
DESIGN CONSIDERATIONS (CONT.)
T1 is the time required for the leakage inductance of the flyback transformer to completely discharge its stored energy into the voltage clamp. T1 can be calculated as: T1 = (IPK x LLEAK ) / VOVERSHOOT (7) where IPK is the peak current in the MOSFET at turn-off and LLEAK is the inductance of the flyback transformer measured at winding n1. T2 is the conduction time of the output diode D2 and T is the switching period. From Equation 4 the resistance RAUX or the voltage VAUX can be calculated. Example: calculate the value of RAUX with the following typical values:
IAUX VAUX RAUX D3 V1 + Vn3 _ V T1 T2
CT FB GND RS FEEDBACK VOLTAGE 0
D2 VIN RST + VAUX n3 CAUX VCC CT DRV STABILIZING RAMP 0.98 V n2 + VOUT D3
OC
SWITCH CURRENT SIGNAL
R1
TL431
(a)
(b)
FIGURE 1: TK75001 IN A FLYBACK POWER SUPPLY (a) SCHEMATIC (b) VOLTAGE AT FEEDBACK PIN
VOUT = 12 V LLEAK = 2 H IAUX = 18 mA n1 = 31
VD2 = VD3 = 1 V VOVERSHOOT = 20 V T2 = 2 s n2 = 6
IPK = 1 A VAUX = 13.5 V T = 5 s n3 = 7
CT
CAUX
n3
VCC
T
Equations 5, 6 and 7 yield V1 = 19.7 V, V2 = 15.2 V, and T1 = 100 ns. Substituting those values into Equation 4 and solving for RAUX yields: RAUX = 20.6
DRV
FB GND
Rounding the result to the nearest 5% standard value gives RAUX = 20 .
FIGURE 2: SUBCIRCUIT FOR CALCULATING THE VALUE OF RAUX
January 1999 TOKO, Inc.
Page 9
TK75001
APPLICATION INFORMATION
SELF-BIASED POWER SUPPLY WITH CONSTANTFREQUENCY CURRENT-MODE CONTROL Figure 3(a) shows the TK75001 IC in the typical application: a flyback converter with self-bias and constant-frequency current-mode control. Figure 3(b) shows the FB Pin voltage. In the converter, the voltage-error amplifier (a TL431 shunt regulator IC) is located at the output side and the error signal is transmitted to the input side through the optocoupler OC. Three signals are added together at the FB Pin: 1)the feedback voltage that develops across the resistor R1, 2) the switch current signal, and 3) the stabilizing ramp. In each cycle, the MOSFET switch is turned off when the sum of those three signals reaches 0.98 V.
D2 VIN RST + VAUX n3 CAUX VCC CT DRV STABILIZING RAMP 0.98 V
TL431
sense resistor of the converter. In voltage-mode control, that resistor is connected to ground. In voltage-mode control, overload protection can be realized by adding a simple circuit to the control IC, as shown in the figure. The PNP transistor Q1, turns on and pulls up the feedback pin when the switch current times the resistance of the sense RS reaches the threshold set by the resistive divider R2 and R3 and the base-emitter voltage of Q1.
VIN VAUX
+
OC VCC CT DRV R2 0.98 V
D3
FB GND
R3
OC
PWM RAMP
+ VOUT
Q1
RS
FEEDBACK VOLTAGE 0
n2
R1
CT FB GND
OC
SWITCH CURRENT SIGNAL
RS
FEEDBACK VOLTAGE 0
(a)
(b)
R1
TL431
(a)
(b)
FIGURE 4: TK75001 IN A VOLTAGE-MODECONTROLLED CONVERTER WITH ADDITIONAL CYCLE-BY-CYCLE CURRENT LIMIT (a) SCHEMATIC (b) VOLTAGE AT FEEDBACK PIN POWER SUPPLY WITH CONSTANT OFF-TIME CURRENT-MODE CONTROL The advantages of constant off-time current-mode control over constant-frequency current-mode control are: 1) there is no need for a stabilizing ramp, 2) the converter is free from subharmonic instability (i.e., there is no need for slope compensation), and 3) the line voltage variation is automatically canceled in buck-derived converters (e.g., the forward converter). Figure 5 shows the implementation of that control method. As can be seen, a transistor Q1 must be added to the controller. Figure 6 shows the timingpin and feedback pin voltages for the TK75001. The transistor Q1 keeps the timing pin at ground potential during the on-time of the switch. Timing begins when the drive output returns to low and Q1 is turned off. The off-time for typical charge and discharge currents and peak and valley voltages is: tOFF = CT x 14 k. January 1999 TOKO, Inc.
FIGURE 3: TK75001 IN A SELF-BIASED FLYBACK CONVERTER WITH CONSTANT-FREQUENCY VOLTAGE-MODE CONTROL (a) SCHEMATIC (b) VOLTAGE AT FEEDBACK PIN
POWER SUPPLY WITH CONSTANT-FREQUENCY VOLTAGE-MODE CONTROL AND CYCLE-BY-CYCLE CURRENT LIMIT Voltage-mode control is free from some of the disadvantages (e.g., subharmonic instability and noise sensitivity) of current-mode control. It is very easy to implement that control method with the TK75001 IC. Figure 4(a) shows the IC in a voltage-mode-controlled flyback converter. Figure 4(b) shows the feedback pin voltage. The only circuit difference between current-mode control and voltage-mode control is in the connection of the resistor R1, that terminates the feedback pin. In currentmode control, that resistor is connected to the currentPage 10
TK75001
APPLICATION INFORMATION (CONT.)
TK75001 IN NON-ISOLATED APPLICATIONS
VIN VAUX
+ VOUT
VCC CT Q1 CT FB GND R1 RS DRV VAUX OC
Figure 7 shows a buck-boost converter with a negative input voltage and a positive output voltage, controlled by the TK75001. The Error Amplifier is a TL431 shunt regulator, and a PNP transistor provides interface between the TL431 and the control IC.
VOUT (+)
TL431 CT
VCC
DRV
FB GND
TL431
FIGURE 5: TK75001 IN A FORWARD CONVERTER WITH CONSTANT OFF-TIME CURRENT-MODE CONTROL
VIN (-)
FIGURE 7: NON-ISOLATED NEGATIVE-TO-POSITIVE CONVERTER
3.2 V CT CT 1.1 V 0
0.98 V FEEDBACK VOLTAGE LEVEL FB FB
FIGURE 6: TIMING PIN AND FEEDBACK PIN VOLTAGES WITH CONSTANT OFF-TIME CURRENTMODE CONTROL
January 1999 TOKO, Inc.
Page 11
TK75001
APPLICATION INFORMATION (CONT.)
TK75001 OFF-LINE APPLICATION EXAMPLE Figure 8 shows an off-line, universal input, 12 W power supply. The TK75001 is the controller IC for a flyback converter with self-bias and constant-frequency, current-mode control. The TK75001 drives the MOSFET directly to switch the flyback transformer. Feedback is accomplished by means of a TL431, configured as a secondary side error amplifier and voltage reference, driving an opto-coupler for isolation.
RB155 1 mH RM4
1.5 mH 0.2 A
+ 2A 22 F 400 V
1M 0.25 W FMMTA42 1M 0.25 W 0.1 F 400 V
24 k 0.5 W
0.001 F 400 V
6CWF20F 16 KCO17L FMMTA42 1N4148 FMMT2222A 0.01 F n3 n1 n2 330 pF 100 V + 330 F 16 V RM6-N67 AL250 100 0.5 W + 330 F 16 V
FERRITE BEAD
+ 82F 25V 12 V 1A
85-265 VAC 47-440 Hz
620 BYV26CPH + 82 F 25 V
n1 = 31, AWG28 n2 = 6, triple insulated, AWG24 n3 = 7, AWG34
VCC CT 220 pF FB GND 0.047 F 1.8 k 1.2 0.25 W TK75001 15 DRV IRFRC20 CNY17-2
470
4.75 k 1%
220 pF 50 V
470 4.7 k 0.01 F
220
TL431
1.24 k 1%
FIGURE 8: OFF-LINE, UNIVERSAL INPUT, 12-WATT POWER SUPPLY
Page 12
January 1999 TOKO, Inc.
TK75001
PACKAGE OUTLINE
Marking Information
Marking 75001
DIP-8
8 5 Marking Lot Number
TK75001
6.4
Country of Origin
1
4
9.5
3.3
0.5 min
3.3
+ 0.3
3.8
+ 0.3
0.25
e + 0.15 - 0.05
+ 0.15 - 0.05
e1
7.62
0~
15
2.54
0.46
0.25
M
Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified)
Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864
TOKO AMERICA REGIONAL OFFICES
Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375
Visit our Internet site at http://www.tokoam.com
The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc.
January 1999 TOKO, Inc.
(c) 1999 Toko, Inc. All Rights Reserved IC-120-TK75001 0798O0.0K
Page 13
Printed in the USA

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